Although indium-phosphide compound semiconductor has a lower Schottky barrier height than that of gallium-arsenide compound semiconductor, it is well known in the art that indium-phosphide compound semiconductor is advantageous over gallium-arsenide compound semiconductor in that indium-phosphide compound semiconductor is larger in saturation velocity and in thermal conductivity than gallium-arsenide and that indium-phosphide compound semiconductor is smaller in ionization coefficient than gallium-arsenide. For this reason, research and development efforts are underway toward applying an indium-phosphide compound semiconductor crystal to a material such as, for example, an indium-phosphide semi-insulating substrate or an indium-phosphide active layer for a ultra-high-cutoff frequency high-power semiconductor device or a ultra-high-speed semiconductor device.
In general, there are three types of strutures for field effect transistors using compound semiconductor material, i.e., MES (metal-semiconductor) gate structure type, MIS (metal-insulator-semiconductor) gate structure type and a p-n junction type. A typical example of the MES gate structure type field effect transistor is illustrated in FIG. 1 and comprises an indium-phosphide semi-insulating substrate 1, an indium-phosphide active layer 2 grown on the upper surface of the semi-insulating substrate 1, a metal gate electrode 3 formed on the active layer 2 and source and drain electrodes 4 and 5. The metal gate electrode 3 is formed of aluminum, and the indium-phosphide active layer 2 provides a metal-semiconductor contact with a Schottky-barrier height of about 0.3 to 0.4 eV. Another MES gate structure type field effect transistor is disclosed by J. S. Barrera et al in "InP Schottky-Gate Field-Effect Transistors", IEEE Transaction on Electron Devices, vol. ED-22, No. 11, November 1975.
FIG. 2 shows a conventional MIS gate structure type field effect transistor which comprises an n.sup.+ indium-phosphide semi-insulating substrate 11, an indium-phosphide contact layer 12 partially removed to expose the semi-insulating substrate 11, a gate insulating film 13 of silicon dioxide deposited on the exposed surface of the semi-insulating substrate 11, a gate electrode 14 provided on the gate insulating film 13, and source and drain electrodes 15 and 16 formed on the contact layer 12. Another MIS gate structure type field effect transistor is disclosed by D. L. Lile et al in "n-Channel Inversion-Mode InP M.I.S.F.E.T.", Electron Letters, Sept. 28 1978, Vol. 14, No. 20, pages 657 to 659.
The prior-art MES gate structure type field effect transistors have a problem in reverse current flowing between the metal gate and the drain as described in the above paper written by J. S. Barrera et al. This is because of the fact that the MES gate structure type field effect transistor has a relatively low Schottky-barrier height between the gate electrode and the active layer. The MES gate structure type field effect transistor further has a problem in gate break down voltage. On the other hand, the prior-art MIS gate structure type field effect transistor does not have the problems in reverse leakage current and low gate break down voltage; however, another problem is encountered in the operation mode and drift of channel current. Namely, the MIS gate structure type field effect transistor has a large amount of surface states which result in pinning of Fermilevel, so that the MIS gate structure type field effect transistor can usually provide only a normally-off type device, (which is reported in the above mentioned paper written by Lile et al). As to the p-n type field effect transistor, it is possible to fabricate both the normally-on and normally-off types; however, a large amount of leakage current takes place across the p-n junction.